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#3343 | Link | |
Registered User
Join Date: Jan 2014
Posts: 2,479
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Quote:
By the way, looking at the download counts, the Windows ARM version has more downloads than the XP-specific one. I suppose this is just out of curiosity, since plugin support is quite limited, to say the least. |
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#3344 | Link | |
Broadcast Encoder
Join Date: Nov 2013
Location: Royal Borough of Kensington & Chelsea, UK
Posts: 3,236
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Quote:
![]() About ARM, Windows on ARM has very limited adoption but the laptops are definitely out there. A friend of mine tried it. It's definitely faster than running the x86 version translated on the fly to ARM, but the problem with the ARM version of Avisynth is that you can't have the ARM frameserver run natively and the x86 incompatible plugins run via the translation layer, rather everything has to be ARM (running natively) or x86 (running via the translation layer). You can't mix and match, which is a bummer. By the way, my use case for ARM was different as I was trying to see if I could save some bucks on AWS by running c6g.2xlarge instances (8c/8th 16GB of RAM) powered by a Graviton 2 ARM host instead of using the c6i.2xlarge instances (8c/8th 16GB of RAM) powered by an Intel Xeon 8375C x86_64 host. $0.3648 (x86) - $0.2918 (ARM) = $0.073 per hour which corresponds to a 20% saving / reduction. So, if the ARM version manages not not be 20% slower in encoding it will save some pennies on my Avisynth farm. |
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#3345 | Link | ||
...?
Join Date: Nov 2005
Location: Florida
Posts: 1,482
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Quote:
Clearly one of the libraries in the DevIL dependency chain has issues even when you use -T v141_xp to build all of them. Quote:
Not to mention whether it applies to a library loading other libraries (like AviSynth+ and its relation to its plugins) vs. an application loading a library (like FFmpeg loading the AviSynth+ core) is something I don't think I've seen a definitive answer to. What I remember of the tests I attempted is that it didn't work in either case, but that was sometime between July-October of last year. |
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#3346 | Link |
Registered User
Join Date: Jul 2018
Posts: 1,335
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While testing different SIMD versions of processing functions some feature of SetMaxCPU() found with VirtualDub: It does not switch CPU type if 'reload (F2)' script. To really switch CPU type and SIMD functions, full VirtualDub process restart is required.
I do not not know how it works with other editors with avisynth.dll loading like AVSpmod. Test script: Code:
SetMaxCPU("something") version Info() Last edited by DTL; 11th May 2025 at 18:10. |
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#3347 | Link |
Registered User
Join Date: Oct 2001
Location: Germany
Posts: 7,700
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As a side note: It really is annoying that sometimes default plugins are in plugins/plugins+/plugins64/plugins64+ when using files_only.
(I ended up loading those plugins manually from a separate folder, to not having to check where the plugins are located on the release.) => I'm fine, but not to confuse others, maybe just stick with 'plugins' and that's it. |
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#3349 | Link |
Acid fr0g
Join Date: May 2002
Location: Italy
Posts: 2,967
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Is there any good samaritan to build AVS+ version of DFTTest2?
I've asked WolframRhodium who kindly refused. Wouldn't be so bad to have a GPU accelerated version of DFTTest. @pinterf? @anyone? Thanks for any effort.
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@turment on Telegram |
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#3350 | Link | |
...?
Join Date: Nov 2005
Location: Florida
Posts: 1,482
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Quote:
Only 3.5.0 deviates from the norm concerning the plugins[+|64|64+] naming, and given this post from shortly after release, it appears that I hadn't prepared a filesonly package for 3.5.0, so it was added after the fact, presumably by pinterf. GitHub seems to have done something to the file timestamps for anything before mid-December 2021, so I can't see exactly when in relation to the release that the 3.5.0 filesonly was uploaded. All of the other release filesonly archives follow the same pattern, because I just copy the contents of the Output/ directories MSVC creates directly into an AviSynthPlus_VERSION_DATE-filesonly directory, under the relevant build architecture (x64, x64-xp, x86, x86-xp). There have been a couple of times the architecture name differed (3.4.0 used 'amd64' and 'i686', 3.7.0 used a slightly more verbose 'x86-64|-32[_xp]'), but that was it. arm64 test builds were present in the packages for 3.7.0, 3.7.1, and 3.7.2, but was skipped in 3.7.3, IIRC because it was languishing with virtually zero discussion around it (logical, because it was *only* in the filesonly package and did not have an installer). arm64 returned in 3.7.4 and 3.7.5 once we actually did introduce an installer, but - as I've mentioned in other posts - part of that mainlining of the WinARM installer was changing how we build for that platform, so the arm64 directory on 3.7.4 and 3.7.5 is laid out completely differently from the earlier test builds. |
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#3351 | Link |
Banana User
Join Date: Sep 2008
Posts: 1,140
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One script had me scratching my head for half an hour because it was producing unexpected, weird effects, all due to a missing dot...
Why this doesn't produce error, it ignores everything on the line after missing dot and outputs RGB: Code:
BlankClip() m=BlankClip().trim(0,-1)ConvertToY8 m Code:
m=BlankClip().trim(0,-1)ConvertToY8 m Code:
BlankClip().trim(0,-1)ConvertToY8
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#3352 | Link |
Formerly davidh*****
Join Date: Jan 2004
Posts: 2,683
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IIRC, if the parser runs into something that otherwise be unexpected, it assumes it's the start of a new statement.
So your first code is equivalent to: Code:
BlankClip() # implicit last m=BlankClip().trim(0,-1) ConvertToY8 # this converts the implicit last cliip m Code:
m=BlankClip().trim(0,-1) ConvertToY8 # no implicit last; error m Code:
BlankClip().trim(0,-1) ConvertToY8 Code:
a=1b=2 foo=3bar=10foo a=1a2a Last edited by wonkey_monkey; 18th May 2025 at 22:54. |
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#3354 | Link | ||
Avisynth language lover
Join Date: Dec 2007
Location: Spain
Posts: 3,442
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Quote:
To clarify, 'unexpected' here means a character that cannot legally continue the current statement. Quote:
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#3355 | Link |
Registered User
Join Date: Jul 2015
Posts: 898
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Has avisynth been permanently removed from ffmpeg?
https://github.com/FFmpeg/FFmpeg/com...5b75147eac79ec |
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#3359 | Link | |
Registered User
Join Date: Jul 2015
Posts: 898
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Quote:
https://github.com/HomeOfAviSynthPlu...orks/releases/ https://github.com/HomeOfAviSynthPlu...76b7a4ec60b850 Modified ffmpeg? Probably yes. |
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#3360 | Link |
Registered User
Join Date: Jul 2018
Posts: 1,335
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Some sad information for Personal Computer users with current AVS+ filters and frame cache design. I asked a question at stackoverflow https://stackoverflow.com/questions/79633556/ the answer is: We still can not use all 32/64bit address space for software design if we need high performance computing. The only usable with best performance is address space of the size of CPU cache. It is only about 10 MBs of 10ths of MBs typically on top consumer CPUs (except Xeon MAX with HBM RAM onboard).
As answers shows - there still no standard way for software to skip data writing to RAM after generation inside the CPU core. (maybe some hacks with cache coherency control still exist ?) . Even if it is temporal data exchange in between AVS filters and no more consumer of this data exists in the future. It is the use case of a simple filter chain (without splitting of output to several consuming filters). This causes the main performance impact: Each frame in AVS cache has its own virtual address space range. This means total address space used by AVS is much larger than CPU cache size if we process SD frames totally cacheable even with several threads running. If we only have 1 source buffer and 1 dest buffer to process in between all filters in a chain (of unlimited length). But if each frame buffer of each intermediate frame in AVS+ cache has its own buffer and number of frames is Nxthreads_number for each connection between filters - this causes the total amount of virtual address space used to be much larger than the CPU cache size. And with cycling processing of all frame buffers CPU produces data for each buffer and stores it first in some levels of fast cache. But production rate may be much higher than the cachelines storage rate to RAM via slow bus. This causes a quick exhausting of free cache lines and total CPU stall doing nothing and waiting for old frames to be downloaded from cache to RAM. CPUs do not have the right to overwrite still not saved to RAM cache lines with different virtual address data. This will cause data loss for later reading from these addresses. The only legal way to increase performance in such host design - to send overwrite instructions to the same virtual addresses. This will legally update data in cache at the full write cache performance and do not cause CPU stall of the execution. The rest of data may be slowly downloaded into slow host RAM if time slots on the host RAM bus are present. Typically it is temporal data in between filters and no need for anyone more so can be skipped completely after the sink filter reads it all from cache. This means general ideas to AVS filters and core design: 1. Use in-place transform filter design if possible (non-resizing and non-spatial non-temporal filters like Levels/Tweak/ColorYUV). 2. Stop using many frames cache (make an option for script writers ?) in between chained filters if possible and reuse a low number of allocated buffers (better only 2 buffers - source and dest and reassign at the next filter call for 1 input and 1 output filter or send pointer to trans in place filter). Need to test in debugger what happens if we set Prefetch(N,1) or even Prefetch(N,0) and make a script with a sequence of transform in place filters. 3. Make transform in place copies of filters where possible and instruct the filter manager of AVS core to use these filters with a single virtual address space allocated buffer in all filter chain while possible. Also if there will be no usable (hacky) solution it looks we need to send request to intel and AMD for new instruction extension at least for SIMD like _mXX_loadu_invd(addr) of simply load data from addr and invalidate cache line with this addr. Though it is easy to do only for cache line aligned loads and if load full cache line only (so usable for AVX512 with 64bytes load and from L1D only with 64 byte cache line size). I still hope some general solution exists like high-level operation of free(addr) or free_invd(addr) with also invalidating all cachelines containing addresses from memory-allocated area (with page-size granularity of 4KB). Though it may be natural if user of high-level language calls free() all data is now can be skipped and every free() call may also invalidate cache and save CPU from store not yet saved data from that memory region virtual addresses. This performance issue is really OS-design level with memory services to applications. It is strange if there is no solution yet. Last edited by DTL; 23rd May 2025 at 16:51. |
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